This invention relates to high speed integrated circuit devices and, in particular, to input/output (I/O) structures for integrated circuits, for example a semiconductor memory device, which allow increased operating frequency relative to conventional structures and have input signal energy transfer characteristics which are optimized to support high data transfer speeds.
Briefly, a semiconductor memory system includes a memory controller or processor, as well as one or more memory devices, such as a dynamic random access memory (DRAM) or static random access memory (SRAM), coupled to a bus. An example of such a system, is illustrated in FIG. 1 wherein memory system 100 includes a plurality of memory devices 110 coupled to a memory controller 130 via a high speed memory bus 120. The high speed memory bus 120 includes a number of signal lines which carry address, data and/or control information between the memory controller 130 and the memory devices 110.
There is a continuous demand for the system memory to provide data at a rate which does not unacceptably impact the operating speed of the microprocessor. Recently, microprocessor speeds have doubled on the average every two years. As microprocessor speeds increase, the speed of the memory bus must correspondingly increase to narrow a performance gap between memory controller 130 and the memory devices 110. Shortcomings currently exist which limit the speed at which the memory bus 120 may operate. In this regard, various parasitic losses on the signal line have a significant impact in limiting the bus for high speed operation. These parasitic losses may relate to physical layout features of, for example, the device packaging, the printed circuit board traces and the device I/O and circuit layouts. In fact, maximizing the performance of the signal line typically requires careful control, adjustment or reduction of all parasitic loss coupled to the bus in the memory system 100.
There are a number of factors which affect the speed of information transfer from the memory bus 120 through I/O circuitry of the memory devices 110. In this regard, as operating frequency of the memory bus 120 increases, the input loss characteristics of the memory device 110 tend to become a more significant factor. That is, as the operating frequency of the memory bus 120 increases, the energy transfer characteristic between the signal line of the memory bus 120 and the coupled memory device I/O structure tends to degrade. This degradation partially stems from the parasitic input resistance of the memory device 110. The equivalent parasitic input resistance of the memory device 110 tends to be dominated by the I/O layout structure of an I/O bond pad and I/O circuitry.
With reference to FIGS. 2A and 2B, a conventional bond pad 200 includes a conductive bond pad layer 210 and a doped region 220 both formed on a semiconductor substrate 230, for example a p-type substrate. A top view of a conventional bond pad 200 is illustrated in FIG. 2A. The bond pad 200 may be implemented on any of a number of integrated circuit devices, for example, a conventional semiconductor memory device. The bond pad 200 allows electrical coupling to an I/O pin (not shown) which, in turn, is coupled to the signal lines of the bus 120.
The conductive bond pad layer 210, formed on a semiconductor substrate 230, typically includes a metal layer, for example, aluminum. The conductive bond pad layer 210 is disposed above the doped region 220, for example, an n− doped region. An insulating layer 240 such as an oxide layer is disposed between the bond pad layer 210 and the doped region 220.
The doped region 220 typically includes an impurity region of opposite conductivity type than that of the substrate 230. This impurity region forms a PN junction with the substrate 230 to prevent or minimize the possibility of a short circuit between the bond pad layer 210 and the substrate 230.
With reference to FIG. 2B, a cross section of the conventional bond pad 200 of FIG. 2A and corresponding lumped equivalent circuit model 245 is illustrated. The lumped equivalent circuit model 245 is a parasitic series capacitance-resistance load which represents the bond pad 200. The lumped equivalent circuit model 245 is considered from the perspective of a corresponding signal line on the memory bus 120 of FIG. 1.
The lumped equivalent circuit model 245 includes a parasitic capacitance 255, a parasitic resistance 265, a parasitic junction capacitance 275, and a parasitic resistance 285. The parasitic capacitance 255 is representative of the capacitive effects due to the bond pad 210, insulating layer 240, and doped region 220 structure. As such, the parasitic capacitance 255 is coupled between a bond pad 210 and a doped region 220.
The parasitic resistance 265 is representative of the resistance inherent in the doped region 220. The parasitic resistance 265 is coupled in series with parasitic capacitance 255.
The parasitic junction capacitance 275 results from the PN junction which exists between the doped region 220 and the substrate 230. Here, the substrate 230 is of opposite conductivity to that of the doped region 220 and, as such, a capacitive effect develops between the doped region 220 and the substrate 230. The parasitic junction capacitance 275 is coupled in series with the parasitic resistance 265 of the doped region 220.
The parasitic resistance 285 represents the inherent resistance of substrate 230 with respect to the distant ground potential supply 295. As such, the parasitic resistance 285 is in series with the junction capacitance 275 and a distant ground potential supply 295.
With continued reference to FIG. 2B, the parasitic resistance 265 of the doped region 220 and the parasitic resistance 285 of the substrate 230 are primarily responsible for the high input loss characteristic of the device when operated at very high frequencies (for example, frequencies greater than 200 MHZ). In addition, these parasitic resistive effects may unacceptably attenuate a signal presented by the signal line which is coupled to the bond pad structure 200 in FIG. 2A.
FIGS. 3A and 3B illustrate an output driver portion of a conventional bi-directional I/O circuit 300. The I/O circuit 300 includes an output driver transistor 310, having a drain coupled to a bonding pad 320. The bonding pad 320 is typically bonded, via a bond wire, to a pin residing external to the packaging of, for example, a semiconductor memory device. The I/O circuit 300 may also include electrostatic discharge (ESD) protection which is illustrated as a pair of reverse biased diodes 330 and 340.
The output driver transistor 310 introduces a parasitic capacitance 355 which is coupled in series with a parasitic resistance 365. The parasitic capacitance 355 and parasitic resistance 365 are both coupled in series between the drain electrode of transistor 310 and a ground potential supply 375.
The parasitic capacitance 355 is primarily due to an inherent PN junction between the drain electrode and the substrate. The parasitic resistance 365 is primarily due to the resistance in the substrate region between the drain regions 400 and tap region 410. These parasitic components, and primarily the parasitic resistance 365, tend to degrade performance of the conventional output driver transistor 310 by decreasing or limiting the signal energy transfer characteristic when operating at high frequencies (for example, greater than 200 MHZ).
It should be noted that the parasitic resistance 365 of the output driver 310 of FIG. 3B may be combined or “lumped” with parasitic resistance 285 observed in the bond pad structure 200 of FIG. 2B to establish an overall input loss characteristic of the I/O structure.
FIG. 3B illustrates a top view of the diffusion and polysilicon layers of a conventional transistor layout of the output driver transistor 310 of FIG. 3A. The transistor 310 includes source regions 380, gate electrodes 390, and drain regions 400. Interconnect layers (not shown), for example polysilicon or metal layers, couple common source regions, drain regions, and gate electrodes in parallel to complete the structure of output transistor 310. In addition, the interconnect layer may also couple a drain electrode of the transistor layout to the bond pad.
The transistor layout of FIG. 3B often includes a tap region 410. The tap region 410 is used to bias a well of the output transistor 310 to a supply voltage, for example, ground potential.
There is a need for an I/O structure for a semiconductor device which facilitates proper, efficient and effective operation at high frequencies when incorporated within a high speed bus based system. In this regard, there exists a need to control or limit parasitic losses in, for example, a memory system, and enhance the frequency response of the signal line.
There is a need to eliminate a high input loss of the integrated circuit device and to reduce the parasitic resistance of the doped region below the bond pad. In this regard, there is a need to reduce the parasitic series resistance between the bond pad, substrate region, and the supply voltage. This may enhance the input signal energy transfer characteristic for the integrated circuit device. In the context of memory systems, this will narrow the performance gap between a memory controller and the memory device.
Lastly, there is a need for an output driver and driver layout with decreased parasitic resistance between the drain region and the source voltage. By decreasing the parasitic resistances resulting from the output driver transistor and driver layout, manageability or control of the overall input loss characteristic is enhanced which thereby provides efficient and effective operation at high frequencies. Such reduced parasitic resistances in an output driver structure may enhance the operation of a memory device which is coupled to a high speed bus.